Cell BE - A Network on a Chip
From Computing and Software Wiki
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==== Synergistic Processing Element ==== | ==== Synergistic Processing Element ==== | ||
| - | The ''Synergistic Processing Element'' ('''SPE''') is the main computational engine for the Cell BE. The SPE is highly optimized for floating point operations. The SPEs are capable of performing a single memory instruction and a single data operation every cycle. A common configuration is 3.2 GHz (with 26,666,666 cycles/sec). The SPE cannot directly access main memory and must request data by a request to the memory controller. The SPE contains 256kB of local store memory where a '''copy''' of the data is kept. The implication of this configuration is that once sufficient data is queued, computation can begin in step with memory transfers. Although there is an initial penalty it is quickly overcome for computations on large data sets. | + | The ''Synergistic Processing Element'' ('''SPE''') is the main computational engine for the Cell BE. The SPE is highly optimized for floating point operations. The SPEs are capable of performing a single memory instruction and a single data operation every cycle. A common configuration is 3.2 GHz (with 26,666,666 cycles/sec). The SPE cannot directly access main memory and must request data by a request to the memory controller. The SPE contains 256kB of local store memory where a '''copy''' of the data is kept. This local store is not accessible by elements other than the SPE it resides on. The implication of this configuration is that once sufficient data is queued, computation can begin in step with memory transfers. Although there is an initial penalty it is quickly overcome for computations on large data sets. |
=== Controllers === | === Controllers === | ||
| + | === Element Interconnect Bus === | ||
| + | The ''Element Interconnect Bus'' ('''EIB''') connects the various elements of the Cell BE to one another. It operates in a manner similar to a high bandwidth token ring network. Communication between elements is performed in packets of 16B, each element potentially receiving 1 packet each cycle. | ||
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==== Memory Interconnect Controller ==== | ==== Memory Interconnect Controller ==== | ||
| - | The Memory Interconnect Controller (MIC) interfaces directly with the main memory of the system. It | + | The ''Memory Interconnect Controller'' ('''MIC''') interfaces directly with the main memory of the system. It receives memory access requests from the PPE and SPEs via the EIB and returns data to the processors in packets via the EIB. |
==== Bus Interface Controller ==== | ==== Bus Interface Controller ==== | ||
| - | + | The ''Bus Interface Controller'' ('''BIC''') is a configurable network interface. It is a Rambus FlexIO card that treats the EIB as a transport layer of a network. It has 2 physical interfaces to the EIB and maps those interfaces to a physical network connection. A common use of this interface is to pair with another Cell BE, thus creating a network of 2 PPEs and 16 SPEs. Memory address translation is handled by the BIC allowing processors on one physical chip to make a memory request to the MIC of the second physical chip. In super-computer systems, this interface is usually connected to a backbone which in turn manages clusters of Cell BEs. | |
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== References == | == References == | ||
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== See Also == | == See Also == | ||
| + | PlayStation 3 | ||
| + | Roadrunner | ||
== External Links == | == External Links == | ||
Revision as of 01:38, 13 April 2009
Network on a chip (NOC) is a paradigm in the design of parallel hardware architecture. It differs from System on a chip (SOC) by featuring generic communication channels between processor elements instead of specialized buses to simplify chip design. Network on a chip systems have the ability to have processing elements operating on different data elements simultaneously without special framework. These characteristics allow better energy-performance characteristics[1]
. The Cell Broadband Engine (Cell BE) is a network on a chip design in production by Sony, Toshiba and IBM (STI). The Cell BE demonstrates these characteristics in a high performance, scalable production architecture.
Contents |
Cell BE Architecture
The Cell BE operates as a network on a chip. The individual elements communicate over a interconnect network which operates in a manner comparable to a token ring network.
Processors
The Cell BE is comprised on 2 primary processor types; 1 Power PC Element and 8 Synergistic Processing Elements.
Power PC Element
The Power PC Element (PPE) is a 64 bit processor responsible for running operating system functions. The PPE controls thread level parallelism, and acts as a controller for the Synergistic Processing Elements (SPEs). It supports vectorized single precision floating point operations, and IBM's quad-precision (long double) floating point format.
Synergistic Processing Element
The Synergistic Processing Element (SPE) is the main computational engine for the Cell BE. The SPE is highly optimized for floating point operations. The SPEs are capable of performing a single memory instruction and a single data operation every cycle. A common configuration is 3.2 GHz (with 26,666,666 cycles/sec). The SPE cannot directly access main memory and must request data by a request to the memory controller. The SPE contains 256kB of local store memory where a copy of the data is kept. This local store is not accessible by elements other than the SPE it resides on. The implication of this configuration is that once sufficient data is queued, computation can begin in step with memory transfers. Although there is an initial penalty it is quickly overcome for computations on large data sets.
Controllers
Element Interconnect Bus
The Element Interconnect Bus (EIB) connects the various elements of the Cell BE to one another. It operates in a manner similar to a high bandwidth token ring network. Communication between elements is performed in packets of 16B, each element potentially receiving 1 packet each cycle.
Memory Interconnect Controller
The Memory Interconnect Controller (MIC) interfaces directly with the main memory of the system. It receives memory access requests from the PPE and SPEs via the EIB and returns data to the processors in packets via the EIB.
Bus Interface Controller
The Bus Interface Controller (BIC) is a configurable network interface. It is a Rambus FlexIO card that treats the EIB as a transport layer of a network. It has 2 physical interfaces to the EIB and maps those interfaces to a physical network connection. A common use of this interface is to pair with another Cell BE, thus creating a network of 2 PPEs and 16 SPEs. Memory address translation is handled by the BIC allowing processors on one physical chip to make a memory request to the MIC of the second physical chip. In super-computer systems, this interface is usually connected to a backbone which in turn manages clusters of Cell BEs.
References
[1]http://en.wikipedia.org/wiki/Network_On_Chip
See Also
PlayStation 3 Roadrunner
External Links
--Adamssw 19:36, 12 April 2009 (EDT)
